Low Power CORDIC Implementation Using Redundant Number Representation

In this paper a niethodolog! for reclucing the power consumption of shift-and-add operations in general and especially of CORDIC stages is presented. The proposed method uses the fuct of simultaneous c a r p generation in rediiiidarit carp-save and signed digit structures to predict the miriimiini necessap hardware effortfor shift-and-add operations. As a carry once generated in a certain hit position carinot “ripple I’ through the adder if using redundant number representation, hurdwnre purty can De switched oti or off depending on the shi8 constant. Simulations have shown, that shift dependent hardkvare iitilization ofparallel implementations leads to monotonicallj decreasing power consumption for increasing shift constants. A CORDIC processor element fiir 16 digit SDNR has heeri iniplemented as a layout and simulated with PowerMill in terms of power consumption.